The present disclosure relates to a differential amplifier and an analog/digital converter making use of the differential amplifier.
In the past, with popular use of digital apparatus, there have been widely utilized analog/digital converters each used for converting an analog signal into a digital signal.
In this analog/digital converter, an input analog signal is compared with reference voltages at a plurality of stages to convert the analog signal into a digital signal. Therefor, a plurality of amplifiers are used.
Thus, the analog/digital converter is designed to make use of amplifiers each having a good characteristic. In particular, as a characteristic of such amplifiers, the analog/digital converter employs a two-stage amplifier having an offset reduction function in order to reduce an important offset voltage.
This two-stage amplifier is constructed by connecting a rear-stage differential amplifier having a variable gain to a front-stage differential amplifier having a fixed gain in series. By increasing and decreasing the gain of the differential amplifier provided at the rear stage, the offset voltage of the differential amplifier provided at the front stage appears to be reduced.
In a differential amplifier disclosed in Japanese Patent Laid-open No. 2006-254419 for example (hereinafter referred to as Patent Document 1), in a reset operation, a load circuit included in the amplifier is put in a diode-connection state decreasing the gain of the amplifier. In a comparison operation, on the other hand, the signal output by the differential amplifier is fed back to the load circuit in a positive feedback operation to increase the gain of the amplifier. Thus, the gain of the differential amplifier can be changed and vice versa without lowering the speed of the operation and without increasing the power consumption.